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ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 1 of 21 1 - 888 - 824 - 4184 features histogram and hough transform calculation four 512 x 9 look - up tables provided to perform user - defined point - wise transformations real - time histogram equalization high data rates 512 x 24 accumulation ram pixel location function the ia64250 is a "plug - and - play" drop - in replacement for the original lsi l64250. this replacement ic has been developed using innov asic?s miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" while ensuring they are compatible with the original ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocume nted features" are duplicated. this data sheet documents all necessary engineering information about the ia64250 including functional and i/o descriptions, electrical characteristics, and applicable timing. package pinout for 68 plcc package: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 2 of 21 1 - 888 - 824 - 4184 pin designator: gnd 1 gnd 18 gnd 35 do.5 52 ci.5 2 vdd 19 startio 36 do.6 53 ci.4 3 vdo.6 20 vdd 37 do.7 54 ci.3 4 vdo.5 21 clk2 38 do.8 55 ci.2 5 vdo.4 22 po 39 di.0 56 ci.1 6 vdo.3 23 iodv 40 di.1 57 ci.0 7 vdo.2 24 dv 41 di.2 58 we 8 vdo.1 25 at 42 di.3 59 regadr.5 9 vdo.0 26 gnd 43 di.4 60 vdd 10 vdd 27 vdd 44 vdd 61 regadr.4 11 reset fp 28 do.0 45 di.5 62 regadr.3 12 gnd 29 do.1 46 di.6 63 regadr.2 13 ry 30 do.2 47 di.7 64 regadr.1 14 cy 31 do.3 48 di.8 65 regadr.0 15 rx 32 do.4 49 ci.8 66 vdo.8 16 cx 33 vdd 50 ci.7 67 vdo.7 17 clk1 34 gnd 51 ci.6 68 pin name grid # pin name grid # pin name grid # pin name grid #
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 3 of 21 1 - 888 - 824 - 4184 block diagram: figure 1 controller acc ram 512 x 24 adder sync shift fp counter lut ram 4 x 512 x 9 adder shift sync y counter x counter marker memory at regadr startio_n resetfp di iodv reset fp ci regadr at rx cx ry cy y x we_n lutout sat sel lutdata lutaddr lut do hclr ramdata ramaddr vdo mode out_sel out_sel mod_ramdata 9 2 24 24 24 9 10 24 9 9 24 9 9 9 2 4 9 6 9 9 2 9 ci 9 dv clock clock clock clock clock clock
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 4 of 21 1 - 888 - 824 - 4184 description the ia64250 performs three separate tasks, histogram generation, modified hough transforms, and pixel location. there are three modes of operation for the ia64250: comp utation, i/o, and initialization. the controller block in the block diagram decodes the instructions and contains the mode registers. after decoding the mode, the controller generates all of the control signals to the rest of the part. these control s ignals include the addresses and input data for the lut and acc rams, the select lines for both the output mux and the shifter, and the reset for the fp counter. this block also controls the clearing of the acc ram. the acc ram stores the video data that is to be output during the i/o mode. this data can be modified, depending on mode, by several methods prior to being output. these methods are described in the computation mode section. the lut ram can store up to four different data modifying function s. these functions are used to modify the video data coming in and access the appropriate data in the acc ram through the acc ram address. this data is then sent out on the do output. during the initialization mode, the functions to be performed are def ined. this is accomplished by setting the values in the mode registers contained in the controller block. during the computation mode, the histogram, hough transform, or pixel location data is computed. data equalization also occurs during this mode if desired. the controller block controls the adders and shifters during this mode to ensure correct data manipulation. this is accomplished through the data stored in the mode registers as well as the dv input. the controller block also generates the addr esses to both the rams. the i/o mode allows data to be transferred to the accumulation ram (acc ram) and/or to and from the look up table ram (lut ram). the user can also update the marker memory during the i/o mode. the marker memory is used to quickly find points of interest on the histogram, hough transform, or accumulated histogram curves. up to seven points of interest can be specified on the grey level axis or parameter axis. the corresponding value on the accumulation axis will then be available . the reverse is also true, where the user can specify accumulation values of interest and obtain the corresponding grey values. the memory map located in the i/o mode description shows the configuration of the data stored in the memory. the transfer of data from an external source to either of the rams is done through either the ci or di input bus. the controller block takes in the data and passes it along to the appropriate ram. the controller block also supplies the ram with the address and control signals needed to write the data. during a data transfer from one ram to the other, the controller block performs a similar task, overseeing the transfer and supplying the necessary control signals and address.
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 5 of 21 1 - 888 - 824 - 4184 i/o signal description: the diagram b elow describes the i/o characteristics for each signal on the ic. the signal names correspond to the signal names on the pinout diagrams provide. i/o characteristics: iodv o when high, acc ram or lut ram data on the do bus is valid. vdo.0 - vdo.8 o lut ram data output (uses clk1). cio.0 - cio.8 i control register and lut input data bus. we i used to strobe data into mode latches when low. regadr.0 - regadr.5 i selects mode latch, marker or maximum registers. at i selects marker and maximum registers when high or mode latches when low. at must be low to access the lut or acc rams via the do bus. clk1 i pixel clock active at rising edge. clk2 i user i/o clock (may be connected to clk1) startio i initiates ram i/o at high to low transition. cx,cy i used to increment x or y counters when high. rx,ry i resets x or y counters(overrides cx, cy) when high. reset fp i resets fp counter when high. po o test pin should be left unconnected.
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 6 of 21 1 - 888 - 824 - 4184 initialization mode: initialization defines the operation of the ia64250. the mode and marker memories store 66 nine - bit words that define the operation of the part and contain marker information. the regadr input is used to select the proper register. data is written over the ci bus and read on the do bus. the at pin controls wh ether data is a mode word or a marker. when at is low, the data written is mode information, which is stored in the mode registers contained in the controller block. when at is high, the data is a marker, and is stored in the marker memory. to prevent e rroneous operation startion should be high, and iodv and dv should be low during initialization. mode register table: a t rega dr r/ w bit location w ci0 ci1 ci2 ci3 ci4 ci5 ci6 ci7 ci8 r do0 do1 do2 do3 do4 do5 do6 do7 do8 0 0 w sel0 sel1 sel2 sel3 lu t0 lut1 sh1 sat testn 0 1 w fn0 fn1 eq io0 io1 hclr0 hclr1 func pdwn marker memory table: at regadr r/w contents 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 3 16 17 18 19 32 33 34 35 36 37 38 39 56 57 58 59 r r r r w w w w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w grey level of maximum acc count bits 0 - 8 maximum acc count bits 0 - 8 maximum acc count bits 9 - 17 maximum acc count bits 18 - 23* test mode, do not access test mode, do not access test mode, do not access test mode, do not access r/w marker 0 grey level bits 0 - 8 r/w marker 0 acc count bits 0 - 8 r/w marker 0 acc count bits 9 - 17 r/w marker 0 acc count bits 18 - 23* r/w marker 1 grey level bits 0 - 8 r/w marker 1 acc count bits 0 - 8 r/w marker 1 acc count bits 9 - 17 r/w marker 1 acc count bits 18 - 23* . . . r/w marker 6 grey level bits 0 - 8 r/w marker 6 acc count bits 0 - 8 r/w marker 6 acc count bits 9 - 17 r/w marker 6 acc count bits 18 - 23* *acc count bit 18 - 23 appears on bit location 0 - 5 respectively
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 7 of 21 1 - 888 - 824 - 4184 mode definition: the controll er block decodes the instructions brought in to the ia64250 on the ci bus, with the regadr input determining which instructions are being read in. the mode memory table shows the configuration of the ci bus encoded instruction depending on the state of re gadr. a brief description of the instruction bits follows: sel(3:0) selects the nine bits of the acc ram to be transferred to the do output or to the lut ram. sel0 sel1 sel2 sel3 sel window 0 1 0 1 0 ? 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 1 2 3 4 15 select bits 0 - 8 select bits 1 - 9 select bits 2 - 10 select bits 3 - 11 select bits 4 - 12 select bits 15 - 23 lut(1:0) defines one of the four 512 x 9 luts as active. sh1 when low, the least significant nine bits of the 10 bit lut and y count sum will a ddress the acc ram. when high, the nine most significant bits of the sum will be used. sat when high, the nine bits selected from the 24 bit acc ram output will be forced to 511 (111111111) if the 24 bit acc ram output contains a 1 in the range of bits from the sel + 9 to 23. otherwise the nine bits selected from the acc ram output will be unchanged. test used for testing when low. should be high for normal operation. fn(1:0) determines the operation performed during the computational mode. fn0 fn 1 function 0 0 1 1 0 1 0 1 modified hough transform computation undefined histogram computation pixel location eq when high, causes the output of the acc ram to be accumulated as it is read. this is commonly used to compute the histogram equalization transfer function. when low, the acc ram output is not modified.
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 8 of 21 1 - 888 - 824 - 4184 io(1:0) control the operations of the acc and lut rams during i/o mode (when the startion signal has been asserted). io0 io1 function 0 0 1 1 0 1 0 1 transfer data from the acc r am to the lut ram read the acc ram read the lut ram write the lut ram hclr(1:0) control the clearing of the acc ram during i/o mode hclr0 hclr1 function 0 0 1 1 0 1 0 1 acc ram cleared when either the acc ram or lut ram is accessed undefined acc ram cleared only when the acc ram is accessed acc ram not cleared during an i/o operation func determines the function performed by the marker processor. when high, each marker circuit within the processor will locate an accumulated count from the acc ra m corresponding to the previously given grey value. when low, each marker will locate the grey value corresponding to a previously given accumulation count from the acc ram. pdwn when high, the acc and lut rams are placed in an inactive mode. should be low for normal operation. memory configurations : the following memory maps specify the configuration of the acc ram and the lut ram in the various computational modes. acc ram histogram mode: grey level memory contents 0 count for grey value 0 1 c ount for grey value 1 . . . . . . . . 511 count for grey value 511
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 9 of 21 1 - 888 - 824 - 4184 acc ram modified hough transform mode: hough transform parameter axis memory contents 0 projection along r = 0 1 projection along r = 1 . . . . . . . . 511 projection along r = 511 acc ram find pixel mode: memory contents address 0 - 8 9 - 17 18 - 23 0 x0 y0 flag 1 x1 y1 flag . . . . n xn yn flag n + 1 0 0 0 . . . . 511 0 0 0 lut ram histogram computation: histogram transfer function memory contents 0 f(0) 1 f(1) . . . . . . . . 511 f(511)
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 10 of 21 1 - 888 - 824 - 4184 lut ram hough transform mode (45 < f 90): address memory contents 0 0*cot f 1 1*cot f . . . . . . . . 511 511*cot f lut ram find pixel mode: memory contents address 0 - 5 6 - 7 8 0 flag for grey value 0 t0 1 flag for grey value 1 t1 . . . . . . . . tag bit 511 flag for grey value 511 t511 not used computation mode: histogram computation: during histogram computation, the acc ram and lut ram form the active elements of the data path. the acc ram is addresse d by the controller block. the acc ram address is the di input signal. the data addressed by the di signal is incremented if the dv input signal is high, otherwise the data is left unchanged. the lut is not used in the computation of the histogram and c an concurrently modify the image by a user - defined transfer function. the di signal addresses the lut and the lut data appears on the vdo output pins two clock cycles later. histogram equalization can be performed in real time. the histogram is stored i n the acc ram. the equalization transfer function must be computed and transferred into the lut ram. then during the next frame as a new histogram is being computed, data will also be equalized in real time and passed to the vdo output pins.
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 11 of 21 1 - 888 - 824 - 4184 hough tran sform computation: during hough transform computation, the acc ram stores the projection image, and the lut ram is loaded with the function listed in the modified hough transform parameterization table. during initialization, the lut is loaded with the ap propriate transfer function to compute either f(x) or f(y). once the lut is loaded, the x and y counters are used to generate the proper memory addresses. the x counter is incremented at each valid pixel and reset at the beginning of each line. the y co unter is incremented at the beginning of each line and reset at the beginning of each frame. the control signals for these two counters are generated in the controller block. as each pixel location along a line is addressed, the grey value at that point is added to the partial sum in the memory location. intensity averaging: another computational mode is possible by generating acc ram addresses differently. an example of this is to compute the average intensity of an image as a function of position. c onsider a 512 x 512 pixel image divided into 256 blocks (16 x 16) of 32 x 32 pixels each. to compute the average intensity, the y counter would be incremented every 32 pixels and reset at the beginning of each line. the x counter would be incremented eve ry 32 lines and reset at the beginning of a frame. the proper addresses will be generated by multiplying the x counter output by 16 (this is done via the lut). after processing, the first 256 locations of the acc ram will hold the accumulated intensity i n each 32 x 32 region. setting sel(3:0) = 10 will give the average intensity in each region. pixel location: pixel location is used to determine the x and y coordinates of up to 64 specific pixels or group of pixels in an image. when performing pixel lo cation, the user first loads one of the luts with a table indicating which pixels are of interest. each pixel in the table is assigned a 6 bit flag that allows the user to distinguish groups of pixels. each time an interesting pixel (as specified in th e lut) is found, the x, y, and flag values are stored in the acc ram at the address given by the fp counter. the fp counter is then incremented. note that only 512 values can be stored at any instance. in the event that more values are stored, the first ram locations will be overwritten. pixel location uses the lut and the x and y counters to store a six - bit code and location information about pixels of interest. the x and y counters hold the coordinates of the grey value on the di pins and are contro lled in the same manner described in the hough transform section. di addresses the lut producing a one - bit tag and a six bit flag associated with the grey value. if the tag bit is high and dv is high the six bit flag and x, y case f r(x,y, f ) lut[i] cx,rx controls cy,ry controls 1a 0 f < 45 x tan f + y itan f x y 1b 45 f < 90 y cot f + x icot f y x 1c 90 f < 135 (ymax - y) cot (180 - f ) + x (ymax - i) cot (180 - f ) y x 1d 135 f < 180 (xmax - x) tan (180 - f ) + y (xmax - i) tan (180 - f ) x y
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 12 of 21 1 - 888 - 824 - 4184 coordinates are stored in th e acc ram. storage space is assigned sequentially as defined by the fp counter. i/o mode: once a computation has taken place, the user reads data from the lut or the acc ram. these operations typically take place during a vertical retrace or some other period when the processor is not busy and at is low. this mode is also to load the lut with the desired transfer function. generally, these operations are controlled by clk2 so that data may be read or written at a different rate than the pixel clock. if the acc ram is accessed, the marker values will be updated. the internal signals hclr(1:0) control whether or not the acc ram is cleared during i/o operations. these values are stored in the mode registers of the controller block during the initializa tion mode. if both hclr0 and hclr1 are high then the acc ram will not be cleared during any i/o operation. if hclr0 is high and hclr1 is low, then each acc ram location will be cleared after it is read. if both hclr0 and hclr1 are low then each acc ram location is cleared when either the acc ram location or the corresponding lut ram location is accessed. read/transfer acc ram: once the histogram has been computed and stored in the acc ram, the user asserts startion low to initiate reading of the data. one data value is read out of the acc ram during each clock cycle of clk2 starting with address 0. the address counter for the acc ram is contained in the controller block. if startio remains low, all 512 data values will be read in sequential address or der and the processor will return to pixel processing mode after 512 clock cycles. if startion is returned high, the i/o mode halts and the user can return to pixel processing operations. when the output flag iodv is high, the processor has placed valid data from the lut or acc rams onto the i/o bus. the user controls the destination of the acc ram data via the io(1:0) bits in the mode registers located in the control memory. code 01 signifies that histogram data will be placed on the do output bus, whi le code 00 will transfer data from the acc ram to the lut ram. in both cases the user can modify the histogram data. by setting the internal eq control bit high, an accumulated histogram will be output. the shifter allows the user to determine which nin e bits of the 24 bit acc ram output will be directed to the do bus and lut ram. the shifter control data is stored in the mode registers. the control signals for the shifter are generated in the controller block. additional control over the output forma t can be obtained via the sat pin in the control memory. when sat is high, the resultant nine bit shifted output will be forced to 511 (111111111) if overflow occurs in the shifter.
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 1 3 of 21 1 - 888 - 824 - 4184 marker circuitry: when acc ram is accessed, the marker circuitry in the marker memory is updated. the user can specify up to seven values of grey level and the associated count will be stored in the mode memory. setting func = 1 in the control memory register will accomplish this. by setting func = 0, the user can specify a particular count and the marker memory will be updated with the last grey value whose count is equal to (or just exceeds) the count of interest. the maximum count, and the grey value which it occurred at, are also updated during each i/o cycle and stor ed in mode memory locations 0 - 3. if the accumulated histogram is being computed, i.e. the eq bit in the mode register is set, then the maximum count register will be equal to the number of pixels scanned, and the grey value will be the maximum grey leve l occurring in the image. reading and writing the lut: data input to and output from the lut ram is also controlled by clk2 and startion. on the falling edge of startion, the i/o cycle is initiated with the lut ram addresses being read or written sequent ially with each cycle of clk2. this process is controlled by the address counter in the controller block. lut read/write operations are defined by the io0 - 1 bits in the control memory. code 10 is used to read the lut ram. data will be read sequentially and output on the do bus. to write the lut ram, code 11 is used in the control memory. input from the ci bus is stored in successive addresses with each cycle of clk2. the lut ram can also be addressed from the di bus. a typical application would be h istogram equalization. the lut would contain the equalized transfer function generated by transferring acc ram data to the lut with eq high. setting the fn0 - fn1 bits for histogram computation configures data from the di bus to address both the acc ram an d the lut. equalized data is then output on the vdo bus. histogram computation is taking place concurrently. in this case clk2 should be connected to clk1 to achieve an equalization rate equal to the pixel rate. i/o sequences: read acc, read lut, tra nsfer acc to lut i/o operations can be divided into two groups: those that end before all 512 elements of the acc or lut ram have been accessed (short cycle) and those that end after all 512 elements have been accessed (long cycle). all i/o cycles are in itiated by a high to low transition on the startion input signal. at must be low in each case. the short cycle is terminated when startion is returned high before all elements of the ram have been read. the first data value appears on the do pins three clk2 cycles after startion goes low. the iodv flag also goes high after three cycles, indicating that the
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 14 of 21 1 - 888 - 824 - 4184 data is valid. after the desired number of memory elements have been read, the user returns startion high. the i/o mode completes three cycles late r and iodv returns low to indicate the end of the i/o operation. as soon as iodv returns low, the processor returns to the pixel processing mode specified by the mode register. the long cycle is terminated without user intervention after all elements of the acc or lut rams have been accessed. again, valid data appears on the do pins three clk2 cycles after startion goes low. in this case, iodv is high for 512 clk2 cycles and goes low after the last ram element has been read. after iodv returns low, sta rtion can remain low or be raised high at any time without affecting the operation of the ia64250. reading acc/lut ram or transfering acc to lut: short i/o cycle: end of long i/o cycle: clk2 startio d0 iodv xxxx xxxx xxxx ram0 ram1 ram2 xxxx xxxx clk2 startio do iodv ram508 ram509 ram510 ram511 xxxx xxxx xxxx xxxx
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 15 of 21 1 - 888 - 824 - 4184 write lut the writing of data into the l ut ram is similar to the operations described above, except that the data to write into the ram is placed on the ci bus when startion is low. however, as described above, the processor will not return to the pixel processing mode until iodv returns low. the net result of this is that the ia64250 enters the i/o mode as soon as the startion pin is pulled low and does not return to the pixel processing mode until iodv returns low. the i/o mode will last n + 3 clk2 cycles, where n is the number of ram elemen ts written. writing lut ram: short i/o cycle: start of long i/o cycle: end of long i/o cycle: clk2 startio ci[7:0] iodv ram0 ram1 ram2 xxxx xxxx xxxx xxxx xxxx clk2 startio ci iodv ram0 ram1 ram2 ram3 ram4 ram5 ram6 ram6 clk2 startio ci iodv ram508 ram509 ram510 ram511 xxx xxxx xxxx xxxx
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 16 of 21 1 - 888 - 824 - 4184 pixel processing (small 2 x 2 image): clk1 ry rx.cy cx dv di vdo i(0,0) i(1,0) i(0,1) i(1,1) xxxx xxxx f(i(0,0)) f(i(1,0)) f(i(01)) f(i(01))
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 17 of 21 1 - 888 - 824 - 4184 ac/dc parameters: military (ta = - 55 to 125 c, vdd = 4.5 to 5.5v). all times in ns. dc charact eristics: specified at vdd = 5v over the specified temperature and voltage ranges 1 . symbol parameter condition min typ max unit vil low level input voltage 0.8 v vih high level input voltage military temperature range 2.25 v iin input current v in = vdd - 150 200 ua voh high level output voltage ioh = - 3.2 ma 2.4 4.5 v vol low level output voltage iol = 3.2 ma 0.2 0.4 v ios output short circuit current 2 vdd = max, vo = vdd vdd = max, vo = 0v 15 - 5 130 - 100 ma ma iddq quiescent supply curre nt 3 vin = vdd or vss 15 ma idd operating supply current tcycle = 50ns 200 ma cin input capacitance any input 5 pf cout output capacitance any output 10 pf notes: 1. military temperature range is ? 55 to 125 c, +/ - 10% power supply. 2. not more than on e output should be shorted at a time. duration of short circuit t est must not exceed one second. 3. in power down mode. symbol parameter min max tcycle minimum clock cycle time 60 tpwh minimum clock pulse width high 28 tpwl minmum clock pulse width low 25 tdis input data setup time 25 0.38 tdih input data hold time 7 2.28 tod output delay 17.78 twc minimum we cycle time 180 tpww minimum we pulse width low 75 tas at address setup time 75 tah at address hold time 75 tcs coefficient setup time 75 tch coefficient hold time 75 tado output delay from address valid 24.53 twd output delay from we 24.53
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 18 of 21 1 - 888 - 824 - 4184 ac characteristics: pixel processing operati on: i/o timing: control memory timing ? writing mode data: clk1 di_dv vdo t od t pwh t cycle t pwl t dih t dis clk2 ci/startio do/iodv t wc t pwh t pwl t od t dih t dis we addr ci at t as t wc t ah t ch t as t pww t cs
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 19 of 21 1 - 888 - 824 - 4184 control memory timing ? reading and writing markers: we addr ci at t as t wc t ah t ch t as t pww t cs
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 20 of 21 1 - 888 - 824 - 4184 packaging information 68 plcc package: 68 plcc, (17x17 pins) : symbol min nom max min nom max a 4.02 5.08 0.165 0.2 a1 2.29 3.3 0.09 0.13 b 0.331 0.53 0.013 0.021 c 0.2 0.008 d 25.02 25.27 0.985 0.995 d1 24.13 24.33 0.95 0.958 e 25.02 25.27 0.985 0.995 e1 24.13 24.33 0.95 0.958 e 1.27 bsc 0.05 millimeter inch d .254x45 1.14x45 e1 e d1 pin 1 identifier a e b see detail a detail a a1 c seating plane
ia64250 data sheet histogram/hough transform processor as of production ver. 01 copyright ? 2000 eng211001219 - 01 www.innovasic.com innov asic customer support: ? the end of obsolescence ? page 21 of 21 1 - 888 - 824 - 4184 ordering information: part number temperature grade package description ia64250 - plc68m military 68 lead plastic leaded chip carrier cross reference to original manufacturer part numbers: innovasic part number lsi part number ia64250 - plc68 m q l64250jc15 q L64250JC20

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